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a
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807
frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either +5 V or -5.2 V.
FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator--Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery-- No Crystal Required Quantizer Sensitivity: 2 mV Level Detect Range: 2.0 mV to 30 mV Single Supply Operation: +5 V or -5.2 V Low Power: 170 mW 10 KH ECL/PECL Compatible Output Package: 16-Pin Narrow 150 mil SOIC
PRODUCT DESCRIPTION
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee
FUNCTIONAL BLOCK DIAGRAM
CF1 CF2 PIN NIN QUANTIZER DET COMPENSATING ZERO PHASE-LOCKED LOOP VCO THRADJ SIGNAL LEVEL DETECTOR LEVEL DETECT COMPARATOR/ BUFFER SDOUT FDET RETIMING DEVICE CLKOUTP CLKOUTN DATAOUTP DATAOUTN LOOP FILTER
AD807
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD807-SPECIFICATIONS (T = T
A
MIN
to TMAX, VS = VMIN to VMAX, CD = 0.1 F, unless otherwise noted)
Min 2.5 2 0.001 50 5 50 650 180 1 2 100 Typ Max VS 2.5 500 10 Units V mV V V A V V MHz M pF ps 4.0 7.4 25 1.5 10.0 9.0 10.0 0.4 155.52 155 155 156 4 3.2 3.1 2.0 2.0 4.5 0.45 0.45 3000 7.6 1.0 0.67 0.08 0.04 92 4 x 105 2 x 106 4.5 25 -1.2 -2.0 50.1 1.1 1.1 34.5 -1.0 -1.8 156 20 3.5 3.3 40 2.7 mV mV mV s dB dB dB V V MHz MHz MHz Degrees ns ns Degrees Degrees RMS Degrees RMS Unit Intervals Unit Intervals Unit Intervals Unit Intervals dB dB kHz Bit Periods Bit Periods Volts mA Volts Volts % ns ns
Parameter QUANTIZER-DC CHARACTERISTICS Input Voltage Range Input Sensitivity, VSENSE Input Overdrive, VOD Input Offset Voltage Input Current Input RMS Noise Input Pk-Pk Noise QUANTIZER-AC CHARACTERISTICS Upper -3 dB Bandwidth Input Resistance Input Capacitance Pulse Width Distortion LEVEL DETECT Level Detect Range
Condition @ PIN or NIN PIN-NIN, Figure 1, BER = 1 x 10-10 Figure 1, BER = 1 x 10-10 BER = 1 x 10-10 BER = 1 x 10-10
Response Time Hysteresis (Electrical)
SDOUT Output Logic High SDOUT Output Logic Low PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY CAPTURE RANGE TRACKING RANGE STATIC PHASE ERROR SETUP TIME (tSU) HOLD TIME (tH) PHASE DRIFT JITTER JITTER TOLERANCE
RTHRESH = INFINITE RTHRESH = 49.9 k RTHRESH = 3.4 k DC Coupled RTHRESH = INFINITE RTHRESH = 49.9 k RTHRESH = 3.4 k Load = +4 mA Load = -1.2 mA
0.8 4 14 0.1 2.3 3.0 3.0 3.6
2 5 20 4.0 5.0 7.0
27-1 PRN Sequence Figure 2 Figure 2 240 Bits, No Transitions 27-1 PRN Sequence 223-1 PRN Sequence f = 10 Hz f = 6.5 kHz f = 65 kHz f = 1.3 MHz CD = 0.15 F CD = 0.33 F
3.0 3.0
JITTER TRANSFER Peaking (Figure 20) Bandwidth Acquisition Time CD = 0.1 F CD = 0.33 F POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PECL OUTPUT VOLTAGE LEVELS Output Logic High, VOH Output Logic Low, VOL SYMMETRY (Duty Cycle) Recovered Clock Output, Pin 5 OUTPUT RISE / FALL TIMES Rise Time (tR) Fall Time (tF)
Specifications subject to change without notice.
65 223-1 PRN Sequence, T A = +25C VCC = 5 V, VEE = GND VMIN to VMAX VCC = 5.0 V, VEE = GND, TA = +25C
130 2 x 106 5.5 39.5 -0.7 -1.7 54.1 1.5 1.5
Referenced to VCC = 1/2, TA = +25C, VCC = 5 V, VEE = GND 20%-80% 80%-20%
-2-
REV. A
AD807
ABSOLUTE MAXIMUM RATINGS 1 PIN FUNCTION DESCRIPTIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . 500 V
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Pin Narrow Body SOIC Package: JA = 110C/Watt.
OUTPUT NOISE 1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12
Mnemonic DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2 AVEE THRADJ AVCC1 NIN PIN AVCC2 SDOUT VEE
Description Differential Retimed Data Output Differential Retimed Data Output Digital VCC for ECL Outputs Differential Recovered Clock Output Differential Recovered Clock Output Digital VCC for Internal Logic Loop Damping Capacitor Loop Damping Capacitor Analog VEE Level Detect Threshold Adjust Analog VCC for PLL Quantizer Differential Input Quantizer Differential Input Analog VCC for Quantizer Signal Detect Output Digital VEE for Internal Logic
PIN CONFIGURATION
0 INPUT (V) OFFSET OVERDRIVE SENSITIVITY
13 14 15 16
Figure 1. Input Sensitivity, Input Overdrive
SETUP HOLD
t SU
DATAOUTP (PIN 2)
tH
DATAOUTN DATAOUTP
1 2 3 4 5 6 7 8
16 15 14
VEE SDOUT AVCC2 PIN NIN AVCC1 THRADJ AVEE
CLKOUTP (PIN 5)
VCC2 CLKOUTN
AD807
TOP VIEW (NOT TO SCALE)
13 12 11 10 9
Figure 2. Setup and Hold Time
CLKOUTP VCC1 CF1 CF2
ORDERING GUIDE
Model AD807-155BR or AD807A-155BR AD807-155BR-REEL7 or AD807A-155BRRL7 AD807-155BR-REEL or AD807A-155BRRL
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Pin Narrowbody SOIC 750 Pieces, 7" Reel 2500 Pieces, 13" Reel
Package Option R-16A R-16A R-16A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD807 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD807
DEFINITION OF TERMS Maximum, Minimum and Typical Specifications Tracking Range
Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
This is the range of input data rates over which the AD807 will remain in lock.
Capture Range
This is the range of input data rates over which the AD807 will acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error.
Data Transition Density,
Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 1. For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer (650 V at the 1 x 10-10 confidence level). The center of the Zone of Confusion is the quantizer input offset voltage ( 500 V maximum). Input Overdrive is the magnitude of signal required to guarantee correct logic level with 1 x 10-10 confidence level. With a single-ended PIN-TIA (Figure 3), ac coupling is used and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Overdrive. The AD807 Quantizer has 2 mV Sensitivity. With a differential TIA (Figure 3), Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 1 mV peak-to-peak signal appears to drive the AD807 Quantizer. However, the single-ended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the signal being observed.
Response Time
This is a measure of the number of data transitions, from "0" to "1" and from "1" to "0," over many clock periods. is the ratio (0 1) of data transitions to bit periods.
Jitter
This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (PRN Sequence).
Jitter Tolerance
Jitter Tolerance is a measure of the AD807's ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies, the integrator of the AD807 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD807 output will have a bit error rate less than 1 x 10-10 when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it.
Jitter Transfer (Refer to Figure 20)
Response time is the delay between removal of the input signal and indication of Loss of Signal (LOS) at SDOUT. The response time of the AD807 (1.5 s maximum) is much faster than the SONET/SDH requirement (3 s response time 100 s). In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time.
Nominal Center Frequency
The AD807 exhibits a low-pass filter response to jitter applied to its input data.
Bandwidth
This describes the frequency at which the AD807 attenuates sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the AD807 in dB.
This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted. -4- REV. A
AD807
Damping Factor,
AVCC2 DIFFERENTIAL INPUT VBE 0.8V CURRENT SOURCES HEADROOM 0.7V 0.5mA AVEE 400 400
Damping factor, describes the compensation of the second order PLL. A larger value of corresponds to more damping and less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for the AD807 to lock onto input data from its free-running state.
Symmetry--Recovered Clock Duty Cycle
1mA
0.5mA
Symmetry is calculated as (100 x on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its "0" level and its "1" level.
Bit Error Rate vs. Signal-to-Noise Ratio
a. Quantizer Differential Input Stage
1.2V +VBE
5.9k THRADJ 94.6k AVEE
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is shown in Figure 11. Wideband amplitude noise is summed with the input data signal as shown in Figure 4. Performance is shown for input data levels of 5 mV and 10 mV.
VCM 2mVp-p
b. Threshold Adjust
VCC1
EPITAXX ERM504 SCOPE PROBE AD807 QUANTIZER BINARY OUTPUT
IOH 150 SDOUT 150 IOL
VCM
VEE
a. Single-Ended Input Application
VCM AD8015 DIFFERENTIAL OUTPUT TIA +OUT 1mVp-p
c. Signal Detect Output (SDOUT)
VCC2 450 450
SCOPE PROBE AD807 QUANTIZER BINARY OUTPUT
DIFFERENTIAL OUTPUT
-OUT
2.5mA VEE
VCM
b. Differential Input Application Figure 3. (a-b) Single-Ended and Differential Input Applications
POWER COMBINER + DIFFERENTIAL SIGNAL SOURCE + 0.47F PIN 50 D.U.T.
d. PLL Differential Output Stage--DATAOUT(N), CLKOUT(N) Figure 5. (a-d) Simplified Schematics
AD807
POWER COMBINER + - POWER SPLITTER 100MHz FILTER GND NOISE SOURCE 75 1.0F 100 +5V 0.47F 50 NIN
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio Test: Block Diagram
REV. A
-5-
AD807-Typical Characteristic Curves
200.0E+3 180.0E+3 30.000E-3 35.000E-3
RTHRESH = 0
SIGNAL DETECT LEVEL - Volts
160.0E+3 140.0E+3
25.000E-3
RTHRESH -
120.0E+3 100.0E+3 80.0E+3 60.0E+3 40.0E+3 20.0E+3 0.0E+0 000.0E+0
20.000E-3
15.000E-3
10.000E-3
5.000E-3
RTHRESH = 49.9k RTHRESH = OPEN
000.000E+0 5.0E-3 10.0E-3 15.0E-3 20.0E-3 25.0E-3 30.0E-3 35.0E-3
4.4
4.6
SIGNAL DETECT LEVEL - Volts
4.8 5.0 5.2 SUPPLY VOLTAGE - Volts
5.4
5.6
Figure 6. Signal Detect Level vs. RTHRESH
Figure 9. Signal Detect Level vs. Supply Voltage
35.0E-3 RTHRESH = 0
ELECTRICAL HYSTERESIS - dB
8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 4.4 RTHRESH = OPEN RTHRESH = 49.9k RTHRESH = 0
30.0E-3
SIGNAL DETECT LEVEL - Volts
25.0E-3 20.0E-3
15.0E-3
10.0E-3 RTHRESH = 49.9k 5.0E-3 RTHRESH = OPEN
000.0E+0 -40
-20
0
20 40 60 TEMPERATURE - C
80
100
4.6
4.8 5.0 5.2 POWER SUPPLY - V
5.4
5.6
Figure 7. Signal Detect Level vs. Temperature
Figure 10. Signal Detect Hysteresis vs. Power Supply
9.00
1E-1 5E-2 3E-2 2E-2
8.00
ELECTRICAL HYSTERESIS - dB
RTHRESH = 0
BIT ERROR RATE
7.00
1E-2 S 1 1 erfc 22N 2 1E-3 1E-4 1E-5 1E-6 1E-8 1E-10 1E-12
1277 1278 NSN 1279 1276
6.00
RTHRESH = 49.9k
5.00 RTHRESH = OPEN 4.00
3.00 -40
-20
0
20 40 60 TEMPERATURE - C
80
100
10
12
14
16 18 S/N - dB
20
22
24
Figure 8. Signal Detect Hysteresis vs. Temperature
Figure 11. Bit Error Rate vs. Signal-to-Noise Ratio
-6-
REV. A
AD807
30 TEST CONDITIONS WORST CASE: - 40C, 4.5V 25
20
15
10
XFCB's dielectric isolation allows the different blocks within this mixed-signal IC to be isolated from each other, hence the 2 mV Sensitivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD807 quantizer toggles at 650 V (1.3 mV sensitivity) at the input without making bit errors. When the input signal is lowered below 650 V, circuit performance is dominated by input noise, and not crosstalk.
0.1F PIN 13 500 0.1F 500 QUANTIZER INPUT OPTIONAL FILTER FERRITE BEAD 0.1F
PERCENTAGE - %
5
0 1.4
1.5
1.6
1.7 1.8 1.9 2.0 RMS JITTER - Degrees
2.1
2.2
2.3
NIN 12 50 50 3.65k AVCC2 14 0.1F AVCC1 11 0.1F +5V 309 0.1F 0.1F 50 311MHz NOISE INPUT
AD807
Figure 12. Output Jitter Histogram
1E+3
CHOKE "BIAS TEE" 10F
JITTER TOLERANCE - UI
100E+0
VCC1 VCC2
6 0.1F 3 0.1F
10E+0
AD807
1E+0
Figure 15. Power Supply Noise Sensitivity Test Circuit
0.1F PIN 13
SONET MASK 100E-3 10E+0
500 0.1F 500 NIN 12
1E+6 10E+6
QUANTIZER INPUT
100E+0
10E+3 100E+3 1E+3 FREQUENCY - Hz
50
50 3.65k
309 CHOKE "BIAS TEE"
0.1F 50 311MHz NOISE INPUT
AD807
Figure 13. Jitter Tolerance
AVCC2 14
0.1F 0.1F AVCC1 11 0.1F VCC1 VCC2 6 0.1F 3 0.1F
3.0
+5V 10F
PSR - NO FILTER
JITTER - ns p-p
2.0
CMR 1.0
Figure 16. Common-Mode Rejection Test Circuit
Signal Detect
PSR - WITH FILTER
0 0
0.1
0.2
0.4 0.6 0.3 0.5 0.7 NOISE - Vp-p @311MHz
0.8
0.9
1.0
Figure 14. Output Jitter vs. Supply Noise and Output Jitter vs. Common Mode Noise
THEORY OF OPERATION Quantizer
The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with commonmode voltage as high as the positive supply. The input offset voltage is factory trimmed and guaranteed to be less than 500 V. REV. A -7-
The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis.
AD807
PIN NIN
AD807
COMPARATOR STAGES & CLOCK RECOVERY PLL
THRESHOLD BIAS + + ITHR
IHYS
POSITIVE PEAK DETECTOR NEGATIVE PEAK DETECTOR
LEVEL SHIFT DOWN LEVEL SHIFT UP
SDOUT
Figure 17. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 18 for a block diagram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition.
DATA INPUT DET S+1 1 S
A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio. Thus, the 0.06% fractional loop bandwidth sets a minimum acquisition time of 2000 bit periods. Note the acquisition time for a damping factor of one is 15,000 bit periods. This comprises 13,000 bit periods for frequency acquisition and 2,000 bit periods for phase acquisition. Compare this to the 400,000 bit periods acquisition time specified for a damping ratio of 5; this consists entirely of frequency acquisition, and the 2,000 bit periods of phase acquisition is negligible. While a lower damping ratio affords faster acquisition, it also allows more peaking in the jitter transfer response (jitter peaking). For example, with a damping ratio of 10, the jitter peaking is 0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.
Center Frequency Clamp (Figure 19)
VCO FDET RETIMING DEVICE RECOVERED CLOCK OUTPUT RETIMED DATA OUTPUT
Figure 18. PLL Block Diagram
The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. However, with random data, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 27-1 pseudorandom code is 1/2 degree, and this is small compared to random jitter. The jitter bandwidth for the PLL is 0.06% of the center frequency. This figure is chosen so that sinusoidal input jitter at 92 kHz will be attenuated by 3 dB. The damping ratio of the PLL is user programmable with a single external capacitor. At 155 MHz, a damping ratio of 5 is obtained with a 0.15 F capacitor. More generally, the damping ratio scales as (fDATA x CD)1/2. -8-
An N-channel FET circuit can be used to bring the AD807 VCO center frequency to within 10% of 155 MHz when SDOUT indicates a Loss of Signal (LOS). This effectively reduces the frequency acquisition time by reducing the frequency error between the VCO frequency and the input data frequency at clamp release. The N-FET can have "on" resistance as high as 1 k and still attain effective clamping. However, the chosen N-FET should have greater than 10 M "off" resistance and less than 100 nA leakage current (source and drain) so as not to alter normal PLL performance.
1 2 3 4 5 6 N_FET CD 7 8 DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2 VEE SDOUT AVCC2 PIN NIN AVCC1 THRADJ 16 15 14 13 12 11 10 9
AD807
AVEE
Figure 19. Center Frequency Clamp Schematic
CD 0.1 0.15 0.22 0.33
PEAK 0.12 0.08 0.06 0.04
0.02dB/DIV
10
100
1k FREQUENCY IN kHz
10k
20k
Figure 20. Jitter Transfer vs. CD
REV. A
AD807
C1 0.1F R1 100 J1 C3 0.1F DATAOUTN DATAOUTP J2 C4 0.1F J3 C5 0.1F CLKOUTN CLKOUTP J4 C6 0.1F C8 R3 100 C2 0.1F R4 100 R11 154 TP1 R2 100 R9 154 R5 100 R6 100 R10 154 1 2 3 R7 100 R8 100 C7 4 5 6 7 8 R12 CD 154 TP2
50 STRIP LINE EQUAL LENGTH
TP7 TP8
J5 SDOUT C12 0.1F
DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2
VEE
16 R13 301 C9 R16 3.65k R15 49.9 C13 0.1F J6 PIN NIN C14 0.1F J7 C10 10 9 RTHRESH TP6 TP5
VECTOR PINS SPACED FOR RN55C TYPE RESISTOR; COMPONENT SHOWN FOR REFERENCE ONLY
SDOUT 15 AVCC2 14
R14 49.9
PIN 13 NIN AVCC1 THRADJ 12 11
AD807
AVEE
NOTE: C7-C10 ARE 0.1F BYPASS CAPACITORS RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS
NOTE: INTERCONNECT RUN UNDER DUT
C11 TP3 10F TP4 +5V GND
VECTOR PINS SPACED THROUGH-HOLE CAPACITOR ON VECTOR CUPS; COMPONENT SHOWN FOR REFERENCE ONLY
Figure 21. Evaluation Board Schematic
CIRCUIT SIDE 08-002901-02 REV A
INT2 08-002901-08 REV A
INT1 08-002901-07 REV A
SILKSCREEN TOP 08-002901-03 REV A
COMPONENT SIDE 08-002901-01 REV A
SOLDERMASK TOP 08-002901-04 REV A
Figure 22. Evaluation Board Pictorials
REV. A
-9-
AD807
C1 0.1F SDOUT TP7 C2 R1 R2 0.1F 100 100 C3 0.1F C4 0.1F CLKOUTN R8 100 CLKOUTP C5 0.1F R3 100 C6 0.1F R4 100 C8 TP1 R11 154 R12 154 CD TP2 8 CF2 R5 100 R6 100 R9 R10 154 154 R17 3.65k C11 R14 50 R15 50 C12 2.2F R16 301 C13 0.1F
DATAOUTN DATAOUTP
1 2 3
DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1
VEE
16
SDOUT 15 AVCC 14
R7 100
C7 4 5 6 7
PIN 13 NIN AVCC THRADJ 12 11 10 9 TP6 R13 THRADJ TP5 C15 0.1F C14 0.1F C10
AD807
AVEE
GND TP4
C9 10F 5V TP3 1 NC 2 IIN 0.8 A/W, 0.7pF 2.5GHz 3 NC 4 0.1F 0.01F VBYP +VS +OUT -OUT -VS 8 7
0.1F 10F
50 LINE
50 LINE
ABB HAFO 1A227 FC HOUSING NOTES 1. ALL CAPS ARE CHIP, 15pF ARE MICA. 2. 150nH ARE SMT
150nH 15pF
6 5
150nH 15pF
AD8015
NC = NO CONNECT
Figure 23. Low Cost 155 Mbps Fiber Optic Receiver Schematic
Table I. AD807--AD8015 Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Input Power
Average Optical Input Power (dBm) -6.4 -6.5 -6.6 -6.7 -7.0 to -35.5 -36.0 -36.5 -37.0 -38.0 -39.0 -39.2 -39.3
Output Bit Error Rate Loses Lock 7.5 x 10-3 9.4 x 10-4 0 x 10-14 0 x 10-14 3 x 10-12 4.8 x 10-10 2.8 x 10-8 1.3 x 10-5 1.0 x 10-3 1.9 x 10-3 Loses Lock
Output Jitter (ps rms)
<40 <40
Figure 24. Receiver Output (Data) Eye Diagram, -7.0 dBm Optical Input
APPLICATIONS Low Cost 155 Mbps Fiber Optic Receiver
The AD807 and AD8015 can be used together for a complete 155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery, and Transimpedance Amplifier) as shown in Figure 23. The PIN diode front end is connected to a single mode 1300 nm laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W responsively, 0.7 pF capacitance, and 2.5 GHz bandwidth. The AD8015 outputs (POUT and NOUT) drive a differential, constant impedance (50 ) low-pass filter with a 3 dB cutoff of 100 MHz. The outputs of the low-pass filter are ac coupled to the AD807 inputs (PIN and NIN). The AD807 PLL damping factor is set at 7 using a 0.22 F capacitor.
Figure 25. Receiver Output (Data) Eye Diagram, -36.0 dBm Optical Input
-10-
REV. A
AD807
C1 0.1F SDOUT C2 R1 R2 0.1F 100 100 C3 0.1F C4 0.1F J3 R8 100 J4 C5 0.1F R3 100 C6 0.1F R4 100 R11 150 C8 0.1F R12 150 CD 0.1F R5 100 R6 100 R9 R10 154 154 C12 0.1 1 2 3 R7 100 C7 0.1F 4 5 6 7 8 DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2 VEE 16 R16 330 R14 47 R15 47 C14 0.1 C10 0.1 NOISE FILTER 3 C13 0.1
J1 J2
SDOUT 15 AVCC2 14 C11 0.1 PIN 13 NIN AVCC1 THRADJ 12 11 10 9 R13 THRADJ
R17 3.9k 120nH 30pF 30pF
2 1
PIN TIA EPITAXX ERM504
1F
AD807
AVEE
NOTE PIN TIA PIN 4 (CASE) IS CONNECTED TO GROUND
C9 10 +5V
Figure 26. AD807 Application with Epitaxx PIN--Transimpedance Amplifier Module
The entire circuit was enclosed in a shielded box. Table I summarizes results of tests performed using a 223-1 PRN Sequence, and varying the average power at the PIN diode. The circuit acquires and maintains lock with an average input power as low as -39.25 dBm.
Table II. AD807--Epitaxx ERM504 PIN TIA 155 Mbps Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Average Input Power
250mV
50mV/ DIV
Average Optical Input Power (dBm) 0 -3 -10 -20 -30 -32 -34 -35 -35.5 -36 -37.0 -37.6 -38.0
Output Bit Error Rate 0.0 x 10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.0 x 10-10 0.5 x 10-10 4 x 10-6
-10
Output Jitter (ps rms) 29 35 40 37 33 35 36 39 40 41 42 43 50
-250mV 38.12ns
1ns/DIV
48.12ns
Figure 27. Receiver Output (Data) Eye Diagram, 0 dBm Optical Input
250mV
50mV/ DIV
SONET (OC-3)/SDH (STM-1) Fiber Optic Receiver Circuit
A light wave receiver circuit for SONET/SDH application at 155 Mbps is shown in Figure 26, with test results given in Table II. The circuit operates from a single +5 V supply, and uses two major components: an Epitaxx ERM504 PIN-TIA module with AGC, and the AD807 IC. A 120 MHz, third order, low-pass Butterworth filter at the output of the PIN-TIA module provides adequate bandwidth (70% of the bit rate), and attenuates high frequency (out of band) noise.
-250mV 38.12ns
1ns/DIV
48.12ns
Figure 28. Receiver Output (Data) Eye Diagram, -38 dBm Optical Input
REV. A
-11-
AD807
USING THE AD807 Ground Planes AD807 Output Squelch Circuit
Use of one ground plane for connections to both analog and digital grounds is recommended. Use of a 10 F capacitor between VCC and ground is recommended. Care should be taken to isolate the +5 V power trace to VCC2 (Pin 3). The VCC2 pin is used inside the device to provide the CLKOUT and DATAOUT signals. Use of 0.1 F capacitors between IC power supply and ground is recommended. Power supply decoupling should take place as close to the IC as possible. Refer to the schematic, Figure 21, for recommended connections.
Transmission Lines Power Supply Connections
5V
TO VCC1, AVCC, AVCC2 P_FET
1 2 3 BYPASS CAP 4 5 6 7 8
DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2
VEE SDOUT AVCC2 PIN NIN AVCC1 THRADJ
16 15 14 13 12 11 10 9
Use of 50 transmission lines are recommended for PIN, NIN, CLKOUT, and DATAOUT signals.
Terminations
Termination resistors should be used for PIN, NIN, CLKOUT, and DATAOUT signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the PIN, NIN signals should be placed as close as possible to the PIN, NIN pins. Connections from +5 V to load resistors for PIN, NIN, CLKOUT, and DATAOUT signals should be individual, not daisy chained. This will avoid crosstalk on these signals.
Loop Damping Capacitor, C D
AD807
AVEE
Figure 29. Squelch Circuit Schematic
A ceramic capacitor may be used for the loop damping capacitor. Using a 0.15 F, +20% capacitor for a damping factor of five provides < 0.1 dB jitter peaking.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline IC Package (R-16A)
16
9 0.1574 (4.00) 0.1497 (3.80)
PIN 1 1 8
0.2440 (6.20) 0.2284 (5.80)
0.3937 (10.00) 0.3859 (9.80) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0
0.0196 (0.50) x 45 0.0099 (0.25)
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
-12-
REV. A
PRINTED IN U.S.A.
C2044a-2-3/97
A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and data outputs when SDOUT indicates a loss of signal (Figure 29). The VCC2 supply pin draws roughly 61 mA (14 mA for each of 4 ECL loads, plus 5 mA for all 4 ECL output stages). This means that selection of a FET with ON RESISTANCE of 0.5 will affect the common mode of the ECL outputs by only 31 mV.

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